1. Field of the Invention
The present invention relates to a data storage unit, data storage controlling apparatus and method, and a data storage controlling program, capable of storing all data into a memory including a plurality of memory banks and reading a plurality of desired data simultaneously from the memory.
2. Description of the Related Art
FIG. 1 shows a conventional semiconductor memory MY including memory cells MC, word lines WL and bit lines BL and configured so that a memory cell MC will be accessed by specifying a word line WL and bit line BL defining together the memory cell MC and data be read from a memory cell MC in a position where one word line and one bit line, both activated, intersect each other.
In the semiconductor memory configured as above, the same bit line is shared by data on a plurality of word lines. Therefore, since data appearing on the bit line when different word lines WL1 and WL2 are specified will be destroyed as shown in FIG. 2, data on different word lines cannot be accessed simultaneously.
Also, data can be read simultaneously from independent memory banks. By dividing a memory into banks BK1 to BKn as shown in FIGS. 3A and 3B and assigning different addresses to the respective banks, data on a plurality of word lines can be accessed simultaneously. However, data on different word lines in a bank cannot be accessed simultaneously. That is, it is data having been stored from each bank onto the same word line, not any data having been stored on different word lines in the same bank, that can be read simultaneously.
Note that the “bank” referred to herein means a memory unit included in a memory including a plurality of word lines and a plurality of bit lines and whose word line address can be controlled independently.
Conventionally, pattern recognition or the like, for example, is made of image data by recognizing a specific data array included in input data.
The semiconductor memory includes, for example, a buffer memory capable of storing several lines of image data and outputting data in units of a pixel, a data processor including a plurality of processor elements capable of processing data having a width of several bits and which can process data in parallel by the plurality of processor elements, and a control information memory to store matching reference data and control data. Each of the processor elements in the data processor converts a group of image data having the form of a matrix of mainly self-assigned pixels of interest in image data output from the buffer memory, by binarizing the image data group with a threshold, into object data each having a serial-array bit width the processor element can process, and judges if the object data coincides with reference data existent in the same form in the control information memory (cf. Japanese Patent Application Laid Open No. 2003-203236).
It is assumed for example that for raster scan of patterns included in an image and which are to be accessed simultaneously starting at the upper left, a memory is divided into five banks correspondingly to the number of simultaneous accesses, thereby positioning the data as shown in FIGS. 4A to 4F. In this case, the data can initially be accessed simultaneously about five times. However, when the patterns to simultaneously be accessed are positioned as shown in FIGS. 5A to 5F, a plurality of word lines will be accessed in a bank 0 so that no simultaneous access will be possible. For simultaneous access to the data, the latter has to be stored either into another bank or onto the same word line. Some patterns can be accessed simultaneously by selection of appropriate storage locations. For simultaneous access to such patterns, however, the memory has to be divided into so many banks that one of the banks is formed from only one word line.
Also, extraction of a character or pattern from image data will be described as an example of the image data pattern recognition. The character extraction can be made in various manners, but detection of a “T” pattern as shown in FIG. 6 will be explained herebelow as a simple example.
It is assumed here that the image data are stored in a semiconductor memory. To detect the “T” pattern shown in FIG. 6, six data D1 to D6 assigned thereto are read from a semiconductor memory MY. When the read data D1, D2, D3 and D5 are in black while data D4 and D6 are in white, it can be determined that the image data include a hollow “T” pattern. On the contrary, when the data D1, D2, D3 and D5 are in white while the data D4 and D6 are in black, it can be determined that the image data includes a hollow “T” pattern.
If it is unknown where a desired character or pattern exists in the image data, it is necessary to scan over the entire image data, namely, read necessary data sequentially from the semiconductor memory, as shown in FIG. 7, in order to extract the desired character.
Also, for extraction of different characters, it is necessary to select another set of pixel data simultaneously for reading and comparison.
Thus, for extraction of a character or pattern, it is necessary to simultaneously read a plurality of desired data meeting a purpose from image data stored in the semiconductor memory.
Because of the mechanism of the semiconductor memory, however, data recorded on different word lines in the same bank cannot be read simultaneously from the semiconductor memory.
In case necessary data D1 to D3 and data D4 to D6 are stored on the different lines WL1 and WL2, respectively, in the same bank as shown in FIG. 8 for example, the data D1 to D6 cannot be read simultaneously.
FIGS. 9A and 9B show data distribution in an image and in a memory, respectively. As will be known from FIGS. 9A and 9B, a character or pattern can be read simultaneously from the semiconductor memory in one case but cannot in any other case, which depends upon the position of a reference area.
Therefore, even a conventional semiconductor memory has to be divided into a larger number of banks.
However, when the reference area has a size of five by five pixels, for example, as shown in FIG. 10, the required number of memory banks is twenty five (25). The larger the number of banks, the more difficult it is to manage so large a number of banks, which will add to the number of address lines and to the chip area, and lead to an increased power consumption or any other problems.
That is to say, since different addresses have to be assigned to such banks, the semiconductor memory will need a larger-capacity address bus.
Also, the chip area will be larger since as many decoders and selectors are required as the banks.
Further, simultaneous operation of the plurality of banks will lead to a larger power consumption.
Furthermore, the larger the number of data on one word line, the longer the word line will have to be and the longer time access to data on the one word line will take.
In the conventional semiconductor memory, configuration with one word line in one bank will allow simultaneous reading of data. However, this configuration is not practical because the hardware will be applied with a larger load when an extremely larger amount of data has to be stored.
On this account, in the conventional semiconductor memory, a buffer memory and cache memory to provisionally store data read from the semiconductor memory are provided to time-share a plurality of desired data a plurality of times, provisionally store them in the buffer memory and cache memory, and then read the data from the latter.
However, when the number of desired data is larger and data input/output speed is higher, data will be read more slowly. To solve this problem, it has been proposed to provide a buffer memory and cache memory in order to provisionally hold the data. Even with this technique, however, a larger area occupied by such buffer and cache memories will lead to a larger load to the hardware.